please i want the answers of part e ,f and g

f) Draw the waveform for the cis signal in following process fr 50m0%) Clock gen: process begin wait for 10 ns, CLK wait for 20 ns wait; end process clock_ gern 10 ns 8) If you have been asked to write a testbench for your design (for this system), what of the following you should include (5%) Process to generate Stimulus (for the inputs and the outputs), and a Component of your design (Unit under test) (5%) Process to generate clock Process to generate ASREST signal A and B A,B, and C a) b) c) d) e)