load> enable */ For input stimulus, all signals (except clk) change at the negative edge of the clock Counter changes at the positiv edge of the clock Clk 0 means the initial state, set clock period equal to 10 time units and the initial value of clk as 1 Clk # 012 7 10 15 16 24 25 30 clear 000 0 010 1 0 0 load 010 0 0 0 0 0 0 enable 11 0 1 1 0 data in 060 0 0888 4 4 mode 11 000 1″ aria-describedby=”aii”> 01. (30%) Design a universal synchronous 4-bit counter with the following features module universal counter (data in, load, clear, mode, enable, count) input[3:0] data-in; /* initial value of the counter input load; the positive edge of the clock* input clear;/* if clear-1, count[3:0] is reset at the positive edge of the clock* /* if load-l, count[3:0] İs set to data-in[301 at /* clear has the priority over the load signal*/ input mode; otherwise* /* up counting if mode -1, down counting if input enable; *counter counts when enable1* [3:0] count;*counter output*/ /* priority of control signals: clear> load> enable */ For input stimulus, all signals (except clk) change at the negative edge of the clock Counter changes at the positiv edge of the clock Clk 0 means the initial state, set clock period equal to 10 time units and the initial value of clk as 1 Clk # 012 7 10 15 16 24 25 30 clear 000 0 010 1 0 0 load 010 0 0 0 0 0 0 enable 11 0 1 1 0 data in 060 0 0888 4 4 mode 11 000 1