Consider the code below.]

Loop:

fld f0, 0(x1)

fmul.d f4, f0, f2

fsd f4, 0(x1)

fsub.d f4, f10, f14

addi x1, x1, 8

bne x1, x2, Loop // branches if x1 /= x2

Assume the following latencies: (a) fld/fsd: 1 cycle (b) fsub.d: 2 cycles (c) addi/bne: 1 cycle (d) fmul.d: 6 cycles

Execute the code using hardware-based speculation and multiple issue. Show the execution by reusing the table shown in Figure 3.24 below. Assume issue width of 2. (a) Show the status of associated reservation stations, reorder buffer, and registers after issuing the first two instructions in cycle 1.

Read Write Issues xecutes access CDB at Commits at clock at clock at clock lock at clock Iteration number Instructions number number number numbe number Comment 1d x2,0(x1) addi x2,x2,1 sd x2.0(x1) addi x1.x1.8 bne x2,x3.Loop ld x2,0(x1) addi x2.x2.1 sd x2,0 (x1) addi x1.x1.8 bne x2,x3,Loop ld x2.0(x1) addi x2,x2,1 sd x2,0 (x1) addi x1.x1.8 bne x2, x3,Loop First issue Wait for 1d Wait for addi Commit in order Wait for addi No execute delay Wait for 1d Wait for addi Commit in order Wait for addi Earliest possible Wait for 1d Wait for addi Executes earlier Wait for addi 6 6 10 10 10 10 12 12 13 13 10 13 Figure 3.24 The time of issue, execution, and writing result for a dual-issue version of our pipeline with specu- lation. Note that the 1d following the bne can start execution early because it is speculative