All of them plz


2. Consider an instruction pipeline consisting of the following 5 stages. . Instruction Fetch (IF) 2. Instruction Decode and Register Read (ID) 3. Execution operation or calculate effective address (EX) 4. Memory access (MEM) 5. Write result into register (WB) Consider the execution of the following instructions: SUB R2, R1, R3 XOR R7, R2,R5 AND R10, R4, R2 SW R8, Mem [R6+10] ADD R9,R4, R4 Identify the data hazards for executing the above instructions. How many stall cycles are needed to handle these hazards? Show the pipeline timing-diagram for executing these instructions. Explain how to use operand forwarding to reduce the effect of the above data hazards. How many stall cycles are needed if operand forwarding is used? Draw the timing-diagram if operand forwarding is utilized You want to use only software to resolve hazards. Show how to use instruction scheduling (delayed load) to climinate the above hazards. Show the timing diagram after rescheduling a) b) c)